| 摘要: |
| 在满带宽100 MHz条件下，AD9371的收、发采样频偏问题严重，不采用精确的同步定时模块时，在高斯白噪声信道下测试，误码率较调制误差公式erf值偏高。传统的Gardner定时同步算法虽能降低采样频偏，但Gardner算法的实现复杂度太高。针对这对性能和复杂度间的矛盾，给出了一种同步定时模块的现场可编程门阵列(Field Programmable Gate Array,FPGA)简化实现方法。简化后的Farrow滤波器的乘法器与原始的Farrow相比减少50%，环路滤波器占用FPGA资源和传输时延比原环路滤波器都减少了50%以上。将简化后的同步定时模块在AD9371板卡上进行测试，结果表明简化后的同步定时模块与传统的Gardner同步定时模块性能在-30 dBm时误码同时降低到零，性能完全一样，证明此种同步定时方法的等效简化切实有效。 |
| 关键词: 同步定时 Farrow滤波 环路滤波 误差定时检测 |
| DOI： |
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| 基金项目: |
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| A Simplified Method for an AD9371 Wide-band Wireless Timing Synchronization Module |
| LI Haosong,ZHOU Hanbing,LI Mingwei,ZHANG Chuanyuan,QI Yongzhong,MA Xiaokun |
| (Beijing Guodiantong Network Technology Co.,Ltd.,Beijing 100081,China) |
| Abstract: |
| In debugging AD9371,it is found that the sampling clock offset is very large under full 100 MHz bandwidth condition and the bit error rate(BER) is much higher than modulation error function erf value in the white Gaussian noise channel.Although traditional Gardner algorithm is suitable to decrease sampling clock frequency offset,the Gardner timing synchronize module implementation complexity is too high.For the contradiction between performance and complexity,a simplified Farrow filter and loop filter structure in timing synchronize module is given.The simplified Farrow filter reduces the Farrow filter logic resource more than 50% and the simplified loop filter reduces the logic resource squares and delay time by 50% in field programmable gate array(FPGA) chip.The simplified timing synchronize module is tested on AD9371 radio frequency(RF) transceiver board and the test result proves that its BER is the same as that of traditional Gardner algorithm,at -30 dBm signal-to-noise ratio,the BER is decreased to zero,which proves this simplified timing synchronization is effectively. |
| Key words: timing synchronization Farrow filter loop filter error timing detection |
