| 摘要: |
| 针对采用传统边缘存储器结构的概率低密度奇偶校验（Low Density Parity Check，LDPC）译码器中仍存在锁存问题的现象，借鉴全并行Turbo译码器中的多路更新策略，提出了一种增强的变量节点和校验节点双路更新边缘存储器结构。利用双路更新结构引入的增强随机选择特性，可以显著降低概率迭代译码过程中的锁存现象。仿真分析表明，相比于单路更新结构，采用双路更新边缘存储器结构的概率LDPC译码器能够在误比特率接近10-4量级处获得0.4 dB左右的译码性能增益，同时也能够显著降低迭代译码周期数量，提升译码速率。 |
| 关键词: 概率LDPC译码器 边缘存储器 锁存问题 双路更新 |
| DOI： |
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| 基金项目: |
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| A dual-channel updating edge memory for stochastic LDPC decoder |
| WU Tingyong,LIN Yujing |
| (National Key Labotatory of Science and Technology on Communications,University of Electronic Science and Technology of China,Chengdu 611731,China) |
| Abstract: |
| For the latching problem in stochastic low density parity check(LDPC) decoder with traditional edge memory(EM) architecture,an enhanced variable node(VN) and check node(CN) dual-channel updating EM structure is proposed.The new updating structure is inspired from the multi-channel update strategy in fully parallel Turbo decoder.Benefited from the improved random selection property introduced by dual-channel updating structure,the latching times in the stochastic iterative decoding process can be reduced significantly.Simulation results show that,compared with traditional structure,stochastic LDPC decoder with dual-channel updating EM structure obtains about 0.4 dB gain at bit error rate closing to 10-4 in additive white Gaussian noise(AWGN) channel.Meanwhile,a noticeable decrease in number of decoding cycles(DC) is achieved,which means an increase in decoding rate. |
| Key words: stochastic LDPC decoder edge memory(EM) latching problem dual-channel updating |
