| 摘要: |
| 针对八通道采样器AD9252的高速串行数据接口的特点，提出了一种基于FPGA时序约束的高速解串方法。使用Xilinx公司的FPGA接收高速串行数据，利用FPGA内部的时钟管理模块DCM、位置约束和底层工具Planahead实现高速串并转换中数据建立时间和保持时间的要求，实现并行数据的正确输出。最后通过功能测试和时序测试，验证了设计的正确性。此方法可适用于高端和低端FPGA，提高了系统设计的灵活性，降低了系统的成本。 |
| 关键词: 无线数据传输 多通道ADC 串行数据 并行数据 时钟管理 时序设计 |
| DOI： |
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| 基金项目: |
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| Timing design of eight-channel high-speed ADC based on FPGA |
| XU Li-sheng,XU Gen-qian,MA Zheng-xin,SONG Zao-di,JIANG Xiu-bo,ZHOU Dong-dong,QIN Zhi-chao |
| () |
| Abstract: |
| According to the characteristics of high-speed serial data in eight-channel sampler AD9252,a method which is based on time constraint of FPGA is presented.In this method,the Xilinx FPGA is used to receive the sampling serial data.In order to achieve the setup time and hold time of serial-parallel conversion,the digital clock management(DCM) module,location constraints and Planahead are used. The design is verified by functional and timing test.Because the method is suitable for high-end and low-end FPGA,the flexibility of system is improved. |
| Key words: wireless data transmission multi-channel ADC serial data parallel data digital clock management timing design |
