| 摘要: |
| 提出了一种基于FPGA实现高速数字上变频（DUC）的方法。该方
法采用一种新的多相内插滤波器的高效实现结构，利用多相内插滤波器中各分支滤波器间系
数的特点，使多相内插滤波器消耗的乘法器数量减少一半；并采用一种并行结构的数控振荡
器（NCO），可产生高数据率的上变频本振信号。利用该方法为某雷达中频回波模拟器设计
了DUC模块，其输出数字中频信号的数据率可达1.2 Gsample/s，只消耗了少量资源，满足项
目需求。 |
| 关键词: 雷达回波模拟器；高速DUC 高效多相内插滤波器 并行NCO 数字
中频信号 |
| DOI： |
|
| 基金项目:河南省高等学校青年骨干教师基金项目（2011GGJS-212） |
|
| Design and efficient realization of high speed DUC based on FPGA |
| ZHANG Hai-feng,ZHAO Ai-ling |
| () |
| Abstract: |
| This paper proposes an access to the realization of high data rate digital up co
nverter(DUC) based on FPGA. This method adopts a novel implementation structure
of poly-phase interpolation filter and makes use of the characteristic of branch
between filter coefficients to reduce the consumption of multiplier by half. Be
sides, the adoption of parallel processing Numerically-controlled Oscillator(NCO
) can generate high data rate vibration signal. By following these methods, a DU
C module is designed for a certain radar IF echo simulator, which can generate d
igital I
F signal with data rate up to 1.2 Gsample/s. Few resources are consumed and the
program needs are satisfied. |
| Key words: radar echo simulator high speed DUC poly-phase interpo
lation filter parallel processing NCO digital IF signal |
