| 摘要: |
| 使用VHDL硬件语言，在FPGA内部每个总线通道设计一个状态机，
各通道对应配置独立缓存，实现多通道HB6096航空总线数据收发。对制成品进行测试，结果
表明设计合理可靠，模块工作稳定。该设计方法立足于国产化思路，提高了硬件集成度及数
据处理效率，降低了成本，对国内同类航空总线接口国产化设计具有参考作用。 |
| 关键词: 航空总线 状态机 多通道 HB6096 接口设计 |
| DOI： |
|
| 基金项目: |
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| Design of multi-channel HB6096 aviation bus interface based on FPGA |
| LIU Jiang |
| () |
| Abstract: |
| A design which can send and receive multi-channel HB6096 aviation bus data is
introduced. This method uses the VHDL hardware language to implement a state mac
hine in FPGA for every bus channel which has a dependent cache. The test result s
hows that this design is reliable and the designed module works stably. Based on
the localization
ideas, this design can effectively improve the hardware integrated level and eff
iciency of data processing, and reduce the cost. This method may provide guidanc
e for implementing localization of the other aviation bus interfaces. |
| Key words: aviation bus state machine multi-channel HB6096 inter
face design |
