| 摘要: |
| 根据平面腔体谐振模型理论推导出高速嵌入式电路电源平面对阻抗函数关系式，分
析了电源平面对的谐振特性与PCB板材、介质层厚度以及导体平面的电导率之间的关系,得
出可通过减小介质层厚度、使用高介电常数的介质材料以及增加介质损耗等3种方法来抑制
电源平面对的谐振效应，并使用全波仿真方法验证了可行性。从时域仿真了高速电路中的噪
声传播与电源平面谐振的相互关系，结果表明,通过抑制电源平面对谐振阻抗可将电源噪声
减
小至原有结构的15%，从而有效提高系统的电源完整性。 |
| 关键词: 高速嵌入式系统 电源分布网络；电源平面对结构 谐振阻抗 电
源完整性；噪声抑制 |
| DOI： |
|
| 基金项目:武警工程学院军事应用资助项目(WXK2010-04) |
|
| Power Bus Noise Suppression in High Speed Embedded Systems |
| ZHOU Zi-chen,PAN Feng,SHEN Zhen-ning |
| (Department of Electronic Technique, Engineering College of China Armed Police
Force, Xi′an 710086,China;Key Laboratory of the Ministry of Education for Wide BandGap Semiconductor M
aterials and Devices, Institute of Microelectronics,Xidian University,Xi′an
710071,China) |
| Abstract: |
| The analytic expression of power plane pair impedance is proposed based
on the cavity model resonances, the relation functions among power plane pair r
esonant impedance, PCB material, the plane spacing and conductivity of conductiv
e are deducted. Decreasing the space of the planes, using high permittivity and
high loss tangent insulation material are three basic methods to suppress impeda
nce at resonance. The methods are verified based on full wave FEM simulation. Th
e relationship between the noise propagation and plane pair impedance is illustr
ated
through the time domain simulation, and the results show that the power noise is
reduced over 85% compared with conventional powe
r plane by suppressing the impedance at resonance and power integrity is dramati
cally increased. |
| Key words: high speed embedded system power distribution network(PDN) power plane pair stru
cture impedance of resonance p
ower integrity noise suppression |
