| 摘要: |
| 提出了一种基于提升格式，高效、实时实现JPEG2000中9／7双正交离散小波变换虑波器的VLSI结构设计方法。该方法所设计的结构，在保证同样的精度下，大大减少了运算量，整体运算速度高，硬件花费少，存储需求低，硬件利用率达到100％。用Verilog HDL对系统进行了硬件描述，并选用Xilinx公司的xcv50e-cs144-8器件在ISE4．1环境下实现了综合。 |
| 关键词: 离散小波变换 滤波器 提升格式 |
| DOI：10.3969/j.issn.1001-893X. |
| Received:October 28, 2005Revised:March 25, 2006 |
| 基金项目: |
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| Hardware Design of a Multiplierless, High-Performance,9/7 DWT Filter |
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| Abstract: |
| A high-efficient,real-time VLSI architecture is proposed that can perform 9/7 biorthogonal discrete wavelet transform(DWT) in JPEG2000.By using this architecture,the numbers of computing are reduced enormously with the same precision,the whole computation speed is high with less hardware cost and the memory requirement is low,and it can achieve 100% hardware utilization.The algorithm is simulated initially by Matlab,and then is described and simulated by Verilog HDL.It is synthesized by xcv50e-cs144-8 under Xilinx's ISE4.1. |
| Key words: JPEG000 |
