| 摘要: |
| CDMA2000基站以GPS／GLONASS标准秒信号作为整个系统的时钟同步基准，采用一种PLL（锁相环）＋DDS（直接数字频率合成器）＋PLL的结构实现。引入了时钟同步系统的总体方案。着重介绍了由AD9851和LMX2306构成的后级DDS＋PLL的电路设计和参数设置。根据实验结果对该方案的稳定性和适用性进行了分析。 |
| 关键词: CDMA2000系统 基站 时钟同步 锁相环 恒温晶振 电路 |
| DOI：10.3969/j.issn.1001-893X. |
| Received:August 23, 2005Revised:December 14, 2005 |
| 基金项目:中国科学院资助项目;广东省深圳市科技局科研项目 |
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| CDMA2000 BTS Clock Synchronization System and Circuits |
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| Abstract: |
| The PPS received by GPS/GLONASS is regarded as the reference of CDMA2000 BTS. A PLL DDS PLL implementation is adopted. After the whole scheme is presented, the circuit design and parameter setting of DDS PLL are emphasized. Finally the stability and applicability are analyzed according to the experimental data. |
| Key words: CDMA2000 system BTS clock synchronization PLL OCXO circuit |
