| 摘要: |
| 本文介绍了8B/10B编码技术,提出了一种简单、实用的8B/10B编码器的实现方法,并且采用Verilog语言设计了一种通用的软核。通过在FPGA器件上进行测试,电路稳定、可靠,可直接嵌入到需要8B/10B编码功能的收发器电路中。 |
| 关键词: 串行数据传输 8B/10B编码 极性偏差(RD) Verilog语言 |
| DOI：10.3969/j.issn.1001-893X. |
| Received:December 25, 2004 |
| 基金项目:国家科技攻关项目;中国科学院资助项目 |
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| Design and Realization of an 8B/10B Encoder |
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| Abstract: |
| This paper introduces 8B/10B encoding technique,and puts forward a simple and practical realization method of an 8B/10B encoder.Furthermore,a versatile soft-core designed with Verilog is presented. It is tested to be stable and reliable by FPGA devices,and can be directly embedded in transceiver circuit with 8B/10B encoding function. |
| Key words: Serial data transmission,8B/10B encoding,Rrunning disparity(RD),Verilog language, |
