| 摘要: |
| 通过一个13阶线性相位的平方根升余弦滚降FIR数字滤波器的结构设计，介绍了如何应用流水线技术来设计高速FIR滤波器。考虑到FPGA的容量问题，对采用流水线技术之后的FIR滤波器占用的硬件资源进行了分析，得出一些结论。 |
| 关键词: FIR滤波器 流水线结构 数字滤波器 |
| DOI：10.3969/j.issn.1001-893X. |
| Revised:January 28, 2002 |
| 基金项目: |
|
| A Pipeline Architecture for High Speed FIR Filters |
|
| () |
| Abstract: |
| The technique about how to use pipeline architecture to design high speed FIR filters is illustrated through the process of designing a 13-tap FIR digital filter called digital square root raised cosine filter, for filtering the signals without intersymbol interferences. Taking into account of the capacity of FPGA, an analysis of the resources consumed by the FIR filter is made, and based upon the analysis a conclusion is drawn. |
| Key words: FIR filter,Pipeline architecture,Carry save adder,Carry propagate adder,FPGA, |
