| 摘要: |
| 在超大集成电路的设计过程中,库单元绑定是非常重要的一环。它的目标是通过特定的方法，把一组布尔网络表述的逻辑功能能用具体的库单元实现。逻辑分解是这一过程中非常重要的一步，经分解产生的主题图质量的好坏直接影响到最后的设计结果。本文针对主题图的面积优化问题，提出了“再分解”这一新设计方法，该方法采用“逻辑变换”技术，使主题图中门的娄量尽量减少，从而达到减小实际网表面积的目的。 |
| 关键词: 单元库 布尔网络 VLSI 集成电路设计 |
| DOI：10.3969/j.issn.1001-893X. |
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| 基金项目: |
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| Design Approach of Redecomposition for area Optimization |
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| Abstract: |
| Cell-library binding is a very important step during the design of VLSI. The purpose of cell-library binding is to implement the logic functions of a group of Boolean networks by using some library cells. Logic decomposition is significant during the process. The subject-graph which is obtained by logic decomposition directly effects the final result of the design. In this paper, we present a new method named "logic redecomposition" which aims at the area optimization of the subject-graph. Logic transformation technology is used in this method to reduce the number of the gates of the subject-graph. By this way, the area of the netlist will be decreased. |
| Key words: Cell-library,Boolean network,subject graph,logic decomposition, |
