| 摘要: |
| 本文针对传统方法实现的数字锁相环(DPLL)工作速率低的问题,通过对一种典型的DPLL的分析,找出影响其工作速率的主要因素,研究并提出了一种全新的高速实现方法,并在实验室进行了数据传输位同步提取实验。 |
| 关键词: 数据通信 数字锁相环 位同步 |
| DOI：10.3969/j.issn.1001-893X. |
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| 基金项目: |
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| Study of a New High Speed DPLL |
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| Abstract: |
| Aiming at the problem that DPLL made by traditional method is low inspeed. the paper has pointed out the main factors which affect the working speedby the analysis to a typical DPLL. A new implementation method for high speedDPLL is Proposed and studied. The experiment is done for bit synchronization sys-tem in laboratory. |
| Key words: Digital and Data Communication,DPLL,Bit Synchronization, |
