| 摘要: |
| 为解决现场可编程门阵列(Field Programmable Gate Array，FPGA)加速卷积神经网络资源占用率较高、加速效果不理想等问题，在去除进位链的基础上通过查找表(Look-up Table,LUT)编码INIT参数值、优化关键延迟路径等方法改进了基于LUT的无符号8位×8位近似乘法器。相比于同类型乘法器，在相同条件下其面积、CPD(Critical Path Delay)和功耗最高可分别节省约27.2%、154%、60.1%。在此基础上通过重复递归调用和移位排列等方法，将乘数位数扩大到原来的两倍并增添了有符号数字处理模块，提出了一款基于LUT的有符号8位×16位近似乘法器，将其部署至卷积神经网络的卷积层中，与Xilinx(现AMD)公司提供的Multiplier IP核相比，在精度下降2.8%的前提下可以节省约8.62%的卷积面积、约20%的卷积功耗和约22.1%的整体项目FF(Flip Flop)消耗。将其部署至Sobel边缘检测项目中，最高可节省约28.9%的项目面积、32.1%的项目功耗、211%的FF并能保持较高的边缘检测精度。 |
| 关键词: 卷积神经网络 硬件加速 近似乘法器设计 近似容错计算 |
| DOI：10.20079/j.issn.1001-893x.250407001 |
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| 基金项目:辽宁省应用基础研究计划项目（2023-179）；辽宁省研究生教育教学改革研究项目（LNYJG2024198） |
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| Design and Implementation of an FPGA Acceleration-oriented Approximate Multiplier |
| 〖HJx〗YANG Yonghaoa,WANG Yiran,SUI Xinyua,YUE Wenhaob,LIU Enhuaa,PAN Lanlanb,LI Xianga |
| (1a.College of Information Engineering;1b.College of Mechanical and Power Engineering，Dalian Ocean University，Dalian 116023，China;2.College of Software，Shandong University，Jinan 250100，China) |
| Abstract: |
| To address the issues of high resource occupancy and unsatisfactory acceleration performance in accelerated convolutional neural networks on field programmable gate array(FPGA)，a look-up table(LUT)-based unsigned 8-bit×8-bit approximate multiplier is improved by removing the carry chain，encoding the INIT parameter values of the LUT，and optimizing critical delay paths.Compared with those of similar multipliers，about 27.2% of the area，1.54% of the critical path delay(CPD) and 60.1% of the power consumption can be saved.An LUT-based signed 8-bit × 16-bit approximate multiplier is proposed，employing methods such as repeated recursive invocation and shift alignment to double the multiplier bit width，along with adding a signed number processing module.Compared with those of the multiplier IP core provided by Xilinx(now AMD)，about 8.62% of the area，20% of the power consumption and 221% of the flip flop(FF) can be saved，with only 2.8% reduction in accuracy，when deployed in the convolutional layer of a convolutional neural network.Meanwhile，about 28.9% of the area，32.1% of the power consumption and 21.1% of the FF can be saved，while maintaining high edge detection accuracy，when deployed in the Sobel edge detection project. |
| Key words: convolutional neural network hardware acceleration approximate multiplier design approximate fault-tolerant computation |
《电讯技术》编辑部 