| 摘要: |
| 在信号调制过程中，为了缩短载波生成的捷变时间，分析了影响捷变时间的因素。提出了单频信号的并行合成结构，解决了载波频率受现场可编程逻辑门阵列(FPGA)时钟限制的问题。为了解决调制过程中采样频率受时钟约束的问题，给出了矢量信号的正交并行调制结构。通过在FPGA上编写Verilog代码实现了时钟频率为160 MHz、采样率为1.92 Gsample/s的并行矢量信号调制，载波频率为200~300 MHz可变，捷变时间小于35 ns。结果表明，并行载波生成和并行调制的方法在克服系统时钟约束方面有较强的实用性。 |
| 关键词: 矢量信号源 并行载波生成 高速捷变 并行调制结构 FPGA实现 |
| DOI： |
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| 基金项目: |
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| FPGA implementation of an Agile parallel modulation vector signal generator |
| LUO Yijun,LU Dongdong,LI Qin |
| () |
| Abstract: |
| In order to save the frequency shifting time(FST) of carrier in modulation，critical factors of FST are analyzed in this paper.A parallel structure of sinusoidal signal synthsis is proposed to solve the problem that the maximum frequency is limited by field programmable gate array(FPGA) clock.A novel structure is provided in the quadrature modulation of vector signal to solve the problem that the sample time is limited by FPGA clock. By writing Verilog code ，the vector signal modulation in parallel structure is implemented on FPGA，of which the working clock is 160 MHz and the sample rate is 1.92 Gsample/s，the carrier's frequency is variable from 200~300 MHz，and the FST is less than 35 ns. It is proved that the parallel structure in carrier generation and the parallel structure in modulation are practical ways to overcome the restriction of FPGA clock. |
| Key words: vector signal source parallel frequency generation agile frequency shifting parallel modulation structure FPGA implementation |
《电讯技术》编辑部 