| 摘要: |
| 给出了宽带数字射频存储器(DRFM)雷达干
扰机信号处理模块组成框图以及信号处理流程，描述了模块实现的关键技术，特别是在FP
GA中实现高速信号并行处理的方法。该信号处理模块可以提供1 GHz瞬时处理带宽，存
储深度达到2 048 μs，可实现对新体制宽带雷达有效干扰，具有广阔的应用前景
。 |
| 关键词: 雷达干扰机 数字射频存储器 信号处理 高速传输 并行处理 |
| DOI： |
|
| 基金项目: |
|
| Design of signal processor for wideband DRFM radar jammer |
| YANG Chun |
| () |
| Abstract: |
| The composition block diagram and signal pr
ocessing flowchart of the signal processor for wideband digital RF memory(DRFM)
jammer are provided. The key te
chnology of realizing the processor module is described with focus on solution t
o parallel high-speed signal processing
in FPGA.
This module can give 1 GHz processin
g bandwidth and 2 048 μs memory depth. It can jam new system wideb
and radar effectively and has wide applications. |
| Key words: radar jammer DRFM signal processing high-speed transmission parallel processing |
《电讯技术》编辑部 