| 摘要: |
| 论述了一种结构精简且高效的浮点数蝶形运算单元设计，单元内部模块的使用效率接
近100%。采用串行全流水线结构设计，与并行结构相比节省了75%的硬件资源消耗。利用按
时间抽取(DIT)的快速傅里叶变换(FFT)算法，通过VHDL编程实现了以该蝶形单元为基础的
1 024点浮点FFT处理器。QUARTUS II中的仿真结果证明了设计的正确性。该设计已成功应
用于一种音频信号分析仪的信号处理部分。 |
| 关键词: 信号处理 蝶形运算单元 浮点数 快速傅里叶变换 流水线 按时间抽取 |
| DOI： |
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| 基金项目: |
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| Design of a floating-point butterfly unit with simplified structure |
| YU Long-yang,DUAN Wen-wei,LI Shu-jian |
| (School of Electronic and Information Engineering,Beijing University of Aerona
utics and Astronautics,Beijing 100191,China) |
| Abstract: |
| This paper presents an efficient design of butterfly unit with simplif
ied structure.The occupating coefficient of inner modules of the unit is almost
100%. This unit uses a full pipeline structure, which saves 75% of the
hardware resource consumption compared with the parallel structure.A floatingp
o
int FFT processor based on this butterfly unit is realized by using the FFT alg
orithm of DIT(Decimationintime). The simulation results
of QUARTUS II demonstrate the correctness of the design. This design has been s
uccessfully applied in the signal processing part of an audio signal analyser. |
| Key words: signal processing butterfly unit floating point FFT pipeline DIT |
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