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引用本文：

马宇飞,李署坚.锁相式频率合成器的设计与改进[J].电讯技术，2010，50（7）： - . [点击复制]
MA Yu-fei,LI Shu-jian.Design and Improvement of a Frequency Synthesizer Based on Phase locked Loop[J].，2010，50（7）： - . [点击复制]

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锁相式频率合成器的设计与改进
马宇飞,李署坚
0 字体:加大+\|默认\|缩小-
(北京航空航天大学电子信息工程学院，北京 100191)

摘要:

针对目前的锁相式频率合成器分辨能力不高和频率转换时间较长的问题，采用DDS/ PLL组合式频率合成器，信号频率的转换时间最短可达到80 ns；在输出前端采用增益可控放大电路，有效解决了信号输出强度随着频率升高而不断衰减的问题，使输出信号幅度稳定在1～1.05 V之间。详细论述了系统的总体结构、软硬件结构，并给出了实验测试结果。

关键词: 频率合成器锁相环信号发生器增益可控放大器

DOI：

基金项目:

Design and Improvement of a Frequency Synthesizer Based on Phase locked Loop

MA Yu-fei,LI Shu-jian

(College of Information and Electrical Engineering,Beijing University of Aeron autics and Astronautics, Beijing 100191,China)

Abstract:

In allusion to the problem of weak discernibility and long conversion time of p haselocked loop(PLL) frequency synthe sizer,the DDS/PLL combined frequency synthesizer is used, and the frequency coversion ti me is as short as 80ns. By using gaincontrollable amplifier circuit in output p ort, the pr oblem that the intensity of signal will be decaying with the increasing of frequ ency can be solved effectively, and the signal amplitude can stay 1～1.05 V. The sys tem structure,hardware and software composition are detailed.The experimental re sults are also given.

Key words: frequency synthesizer phase locked loop(PLL) signal generator gain controll able amplifier