| 摘要: |
| 在通信双方为同源时钟的前提下,为保证时钟在接口处把所有数据都正确采样进来,利用Altera的综合开发平台Quartus II,实现了采样时钟相位根据输入数据相位自动调整,使采样时钟能找到最佳的采样时间来采样外来数据。任意相位时钟管理器可以产生高精度动态相位的时钟信号。 |
| 关键词: 数字电路设计,时钟系统,相位调整,时钟同步 |
| DOI：10.3969/j.issn.1001-893X. |
| 修订日期：2007-11-02 |
| 基金项目: |
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| Design of an Arbitrary Phase Clock Management System Based on FPGA |
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| Abstract: |
| For the both sides under the homologous clock in communication,in order to ensure that all the interfaces can correctly sample the data entered,a method using Altera's Quartus II integrated development platform is presented in this paper.With this method,a sampling clock phase of the system can adjust arbitrarily based on input data,and the sampling clock can find the best time to sample foreign data.Arbitrary phase clock management devices can produce high-precision dynamic phase of the clock signal. |
| Key words: digital circuit design,clock system,phase adjustment,clock synchronization |
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