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  • 罗 鑫.一种Ka频段高密度高集成瓦式T组件的设计[J].电讯技术,2021,61(3): - .    [点击复制]
  • LUO Xin.Design of a high density and high integration tile-type T module in Ka-band[J].,2021,61(3): - .   [点击复制]
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一种Ka频段高密度高集成瓦式T组件的设计
罗鑫
0
(中国西南电子技术研究所,成都 610036)
摘要:
介绍了一种Ka频段瓦式T组件的设计方法和关键技术。采用多层印制电路板(Printed Circuit Board,PCB)技术,实现了无源网络和馈电网络集成在同一块多层电路板上,滤波功能层和天线一体化集成,利用毛纽扣实现了组件的三维垂直互联。采用互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)工艺与砷化镓(GaAs)工艺相结合的芯片异构集成方案,成功研制出16通道带滤波功能层天线的T组件,体积为22 mm×22 mm×12 mm,质量不超过13 g。与同频段同功能的砖式T组件相比,体积缩减75%,质量降至10%。该组件充分发挥CMOS工艺强大的数模混合集成能力和化合物半导体工艺优异的射频性能,并将两类芯片在平面内直接异构拼装,在集成密度、功能密度、射频性能以及可实现性等多个方面获得了良好的平衡。
关键词:  有源相控阵  Ka频段  瓦式  CMOS  异构集成
DOI:
基金项目:
Design of a high density and high integration tile-type T module in Ka-band
LUO Xin
(Southwest China Institute of Electronic Technology,Chengdu 610036,China)
Abstract:
The novel design method and key technologies of a tile-type T module in Ka-band is introduced.With the multi-layer printed circuit board(PCB) technology,the passive network and the port feed network are integrated on the same layer.The filter and antenna are integrated in one PCB,and the 3D vertical interconnection of components is realized by using the fuzz buttons.The heterogeneous integration scheme of chip is adopt by combining complementary metal oxide semiconductor(CMOS) technology and gallium arsenide(GaAs) technology.A 16-channel T module with filter function antenna is successfully developed.The size is 22 mm×22 mm×12 mm and the weight is less than 13 g.Compared with the brick T module with the same frequency band and function,the size is reduced by 75% and the weight is reduced to 1/10.The T module combines with the powerful capability of digital-analog integration of CMOS process and the excellent RF performance of compound semiconductor technology.The two types of chips are heterogeneous assembled in the plane directly,and a good balance is achieved in many aspects,such as integration density,functional density,RF performance and achievability.
Key words:  active phased array  Ka-band  tile-type structure  CMOS  heterogeneous integration
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