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引用本文：

刘景元.宽带8PSK解调高速数传接收机设计[J].电讯技术，2013，53（3）： - . [点击复制]
LIU Jing-yuan.Design of a high data rate receiver with wideband 8PSK demodulation[J].，2013，53（3）： - . [点击复制]

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宽带8PSK解调高速数传接收机设计
刘景元
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(中国西南电子技术研究所，成都 610036)

摘要:

受卫星信道热噪声、多普勒、畸变影响，传统八进制相位键控（8PSK）接收机性能不佳，速率不高，较少应用于航天测控通信系统。针对这一问题，设计并实现了一种基于FPGA 的航天测控系统宽带8PSK解调高速数传接收机，采用Gardner算法实现时钟恢复，利用基于最大似然估计的鉴相算法完成载波同步，并用分数间隔的并行恒模均衡算法提高接收性能。该技术已应用于某接收系统并实现了600 Mb/s 8PSK信号解调，误码率在1×10-3 ～1×10-8之间时，解调损失与理论值不超过2 dB。宽带8PSK解调高速数传接收机可为我国二代中继系统提供支持。

关键词: 测控通信系统高速数传接收机 8PSK解调载波同步定时恢复恒模均衡 TDRSS

DOI：

基金项目:

Design of a high data rate receiver with wideband 8PSK demodulation

LIU Jing-yuan

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Abstract:

Because of the thermal noise, large Doppler and intersymbol interference in a sa tellite communication link, high data rate receiver(HDR) with 8Phase Shift Keying(8PSK) demodulation is used in tracking and data relay satellite sys tem(TDRSS). A wideband 8PSK demodulation technology is proposed. The technology employs Gardner algorithm as timing synchronizer, Maximum Likelihood(ML) Decision Directed(DD) method as phase detector and a fractionally spaced constant modu lus algorithm(FSCMA) equalization to improve demodulation performance.A recei ver based on the technology is implemented by using field programmable gate arra y (FPGA) and a 600 Megabits per second（Mbps）8PSK signal has been tested. Accor ding to the theoretical approach, the demodulation loss difference between teste d value and theoretical value is less than 2 dB when the Bit Error Rate（BE R） ranges 1×10-3 to 1×10-8. China′s new generation TDRSS can employ the receiver as its wideband 8PSK demodulator.

Key words: TT&C system high data rate receiver(HDR) 8PSK demodulator carrier synchronizat ion timing recovery constant modulus equalizer TDRSS