| 摘要: |
| 提出了一种高速Viterbi译码器的FPGA实现方案。该译码器采用全并行结构的加比选模块和寄存器交换法以提高速度，并且利用大数判决准则和对译码器各个部分的优化设计，减少了硬件消耗。译码器的最高输出数据速率可以达到90Mbps。译码器的性能仿真和FDGA实现验证了该方案的可行性。 |
| 关键词: 卷积码 Viterbi译码器 |
| DOI：10.3969/j.issn.1001-893X. |
| 投稿时间：2005-07-07修订日期：2005-10-28 |
| 基金项目:总参谋部资助项目 |
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| FPGA Implementation of a High-Speed Viterbi Decoder |
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| Abstract: |
| The FPGA implementation of a high - speed Viterbi decoder is presented. In order to improve the speed of the decoder, an all - parallel structure of the add - compare - select unit and the register exchange algorithm are adopted. The hardware resources are reduced by means of the majority rule and some optimizations . The maximal data output speed of this decoder is up to 90Mbps. Simulation and FPGA implementation show that this design is feasible. |
| Key words: FPGA |
《电讯技术》编辑部 