| 摘要: |
| 基于有限域上多项式乘法理论，采用高层次设计方法，采用CPLD实现了GF(2^8)上8位快速乘法器，利用XILINX公司的Foundation Series3．1i集成设计环境完成了快速乘法器的VHDL源代码输入、功能仿真、布局与布线、时序仿真，并用XC9572PC84可编程逻辑芯片验证了该电路设计。该乘法器可以应用于RS(255，223)码编／译码器。 |
| 关键词: 乘法器 GF 时序仿真 VHDL语言 可编程逻辑芯片 XILINX公司 功能仿真 XC 源代码 PC |
| DOI：10.3969/j.issn.1001-893X. |
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| 基金项目: |
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| A VHDL-based Design of a Fast Multiplier in GF(28) |
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| Abstract: |
| Based on the theory of polynomial multiplications in Galois field, an 8-bit fast multiplier in (GF(2~8)) is designed using the higher hierarchy technique, and the VHDL model of the multiplier is presented. The design process such as VHDL entry, functional simulation , place and route, timing simulation and device programming are performed by using the XILINX Foundation Series 3.1i software .The circuit is verified in the XC9572PC84 programmable logic device .The circuit for computing multiplications can be used in RS(255,223) codecs. |
| Key words: Reed-Solomon(RS) code,Galois field,Multiplier,VHDL |
《电讯技术》编辑部 