摘要: |
介绍一种由AD9851和LMX2306构成的DDS PLL结构的锁相环路,具有参数设置灵活、频率稳定度高的优点,根据实验结果对环路指标进行了分析计算。该方案已在实际工程中采用。 |
关键词: 锁相环,AD9851,LMX2306,DDS PLL,频率稳定度 |
DOI:10.3969/j.issn.1001-893X. |
修订日期:2003-02-17 |
基金项目:广东省自然科学基金资助项目(000840) |
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A Phase Locked Loop Composed of AD9851 and LMX2306 |
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Abstract: |
A DDS PLL implementation for clock synchronism is presented, being excellent in parameters setting and frequency stability. Some parameters of the PLLs are analyzed and studied according to the experimental data. This scheme has been used in practical engineering. |
Key words: Phase Locked Loop,AD9851,LMX2306,DDS PLL,Frequency stability |