| 摘要: |
| 为提升在资源受限情况下的嵌入式平台上卷积神经网络（Convolutional Neural Network,CNN）目标识别的资源利用率和能效，提出了一种适用于YOLOv5s目标识别网络的现场可编程门阵列(Field Programmable Gate Array,FPGA)共享计算单元的并行卷积加速结构，该结构通过共享3×3卷积和1×1卷积的计算单元提高了加速器硬件资源利用率。此外，还利用卷积层BN(Batch Normalization)层融合、模型量化、循环分块以及双缓冲等策略，提高系统计算效率并减少硬件资源开销。实验结果表明，加速器在200 MHz的工作频率下，实现的卷积计算峰值性能可达97.7 GOPS（Giga Operations per Second），其YOLOv5s网络的平均计算性可达78.34 GOPS，与其他FPGA加速器方案相比在DSP效率、能耗比以及整体性能等方面具有一定的提升。 |
| 关键词: 卷积神经网络(CNN) 目标识别 YOLOv5s 并行卷积加速结构 |
| DOI：10.20079/j.issn.1001-893x.230216003 |
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| 基金项目:国家重点研发计划（2020YFE0202100） |
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| Design of a YOLOv5s Network Efficient Convolution Accelerator Powered by FPGA |
| LIU Qian,WANG Linlin,ZHOU Wenbo |
| (1.National Space Science Center,Chinese Academy of Sciences,Beijing 100190,China;2.School of Computer Science and Technology,University of Chinese Academy of Sciences,Beijing 100049,China) |
| Abstract: |
| A parallel convolution acceleration structure of field programmable gate array(FPGA) sharing computing unit suitable for YOLOv5s target recognition network is proposed to improve the hardware resource utilization of the accelerator by sharing computing units of 3×3 convolution and 1×1 convolution.Furthermore,strategies such as batch normalization(BN) layer fusion of convolution layer,model quantization,cyclic blocking,and double buffering are used to improve system computational efficiency and reduce hardware resource overhead.The experimental results show that at a working frequency of 200 MHz,the peak performance of convolution calculation can reach 97.7 GOPS(Giga Operations per Second),and the average calculation performance of the YOLOv5s network can reach 78.34 GOPS,which is better than other FPGA accelerator schemes in DSP efficiency,energy consumption ratio,and overall performance. |
| Key words: convolutional neural network(CNN) target detection YOLOv5s parallel convolution acceleration structure |
