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  • 张 博,陶晓旭,刘 宇.一种4 Gsample/s 12 b ADC接口电路中的发送器设计[J].电讯技术,2020,60(10): - .    [点击复制]
  • ZHANG Bo,TAO Xiaoxu,LIU Yu.Design of Transmitter in a 4 Gsample/s 12 b ADC Interface Circuit[J].,2020,60(10): - .   [点击复制]
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一种4 Gsample/s 12 b ADC接口电路中的发送器设计
张博,陶晓旭,刘宇
0
(西安邮电大学 电子工程学院,西安 710121)
摘要:
针对一种4 Gsample/s 12 b模数转换器(Analog-to-Digital Converter,ADC)中的接口电路发送器的设计难度大的问题,基于吉比特收发器(Gigabit Transceiver,GTX),遵循JESD204B子类1标准,设计并验证了一种四字节并行发送器。采用四字节并行方案实现8B/10B编码器和加扰器,将系统时钟由1 GHz降至250 MHz,降低了设计难度;通过添加均衡指示位,提高了电路最大工作频率。基于赛灵思ZC706开发板,完成了该发送器与接收端IP的联合验证。实验结果表明,接收数据与发射数据一致且通道间数据无偏移,该发送器满足4 Gsample/s 12 b ADC接口电路的传输带宽需求。相同处理效果下,相比单字节、双字节设计方案资源占比更少。
关键词:  模数转换器  接口电路  吉比特收发器  发射器设计  四字节并行
DOI:
基金项目:陕西省教育厅服务地方专项计划项目(15JF029);陕西省重点研发计划项目(2017ZDXM-GY-004);西安市科技计划项目(201809174CY3JC16)
Design of Transmitter in a 4 Gsample/s 12 b ADC Interface Circuit
ZHANG Bo,TAO Xiaoxu,LIU Yu
(School of Electronic Engineering,Xi′an University of Posts and Telecommunications,Xi′an 710121,China)
Abstract:
In order to solve the difficulty of designing the interface circuit transmitter in a 4 Gsample/s 12 b analog-to-digital converter(ADC),a four-byte parallel transmitter is designed and verified based on the Gigabit transceiver(GTX) and the JESD204B subclass 1 standard.The 8B/10B encoder and scrambler are realized by using four-byte parallel scheme,which reduces the system clock from 1 GHz to 250 MHz and reduces the design difficulty.The maximum working frequency of the circuit is increased by adding balanced indicator bit.Based on the development board of Xilinx ZC706,the transmitter and the receiver IP are both verified.The experimental results show that the received data is consistent with the transmitted data and there is no offset between channels.The transmitter meets the transmission bandwidth requirements of 4 Gsample/s 12 b ADC interface circuit.Compared with that of single-byte and double-byte design schemes,the resource share is less under the same processing effect.
Key words:  analog-to-digital converter  interface circuit  Gigabit transceiver  transmitter design  four-byte parallel
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