| 摘要: |
| 在基于正交频分复用(Orthogonal Frequency Division Multiplexing,OFDM)的无线系统中，快速傅里叶变换(Fast Fourier Transform,FFT)作为关键模块，消耗着大量的硬件资源。为此，针对于IEEE802.11a标准的无线局域网基带技术，提出了一种低硬件开销、低功耗的基-24算法流水线架构FFT处理器设计方案。在硬件实现上，采用单路延迟负反馈(Single-path Delay Feedback,SDF)流水线架构；为了降低硬件资源消耗，基于新型的改良蝶形架构利用正则有符号数(Canonical Signed Digit,CSD) 常数乘法器替代布斯乘法器完成所有的复数乘法运算。设计采用QUARTUS PRIME工具进行开发，搭配Cyclone 10 LP系列器件，编译结果显示该方案与其他已存在的方案相比，至少节约硬件成本25%，降低功耗18%。 |
| 关键词: 正交频分复用；快速傅里叶变换处理器；改良蝶形架构 CSD常数乘法器；流水线架构 |
| DOI： |
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| 基金项目:河北民族师范学院科学技术研究项目(PT2019026)；河北省承德市科技计划自筹经费项目(201904A075) |
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| Design of a low hardware-cost low power 64-point FFT processor for OFDM applications |
| YU Jian |
| (Department of Physics and Electronic Engineering,Hebei Normal University for Nationalities,Chengde 067000,China) |
| Abstract: |
| In an orthogonal frequency division multiplexing(OFDM) based wireless system,fast Fourier transform(FFT) is critical block as it consumes more hardware resources.Therefore, a low hardware-cost and low complexity radix-24 pipelined FFT architecture is presented for an IEEE802.11a wireless local area network(LAN) baseband.A single-path delay feedback(SDF) architecture is adopted for hardware implementation,and for reducing hardware-cost,the proposed scheme employs a canonical signed digit(CSD) constant multiplier based on modified butterfly instead of common booth multiplier,which achieves complex multiplications.Based on QUARTUS PRIME tool with Cyclone 10 LP device,the compiled result shows that the proposed scheme reduces at least 25% hardware-cost and 18% power consumption compared with the existing schemes. |
| Key words: OFDM FFT processor modified butterfly architecture CSD constant multiplier pipelined architecture |
《电讯技术》编辑部 