| 摘要: |
| 针对窄带物联网物理随机接入信道检测和到达时间估计算法处理数据量大、计算耗时的问题，通过分析接收端检测算法的可并行性和数据相关性，基于可重构阵列处理器提出了一种并行化硬件实现方案。该算法在高层配置参数产生的前导符号和通过前期信道处理后的接收符号具有最大相关性时，将此时的到达时间和残留子载波偏移作为估计指标，通过流水线的方式使用多个轻核处理元（Processor Element，PE）实现并行计算以提高运算效率。实验结果表明，使用6个PE同时调度实现算法的映射，运行了35 985个周期，其性能比单个PE提升36.18%。用可重构多核阵列处理器实现该算法的运行时间相较于用Matlab实现，降低了173.09倍，有效提高了接收端检测算法的运算效率。 |
| 关键词: 窄带物联网 接收端检测 可重构阵列处理器 物理随机接入信道 |
| DOI： |
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| 基金项目:国家自然科学基金资助项目（61802304，61834005，61772417） |
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| Parallel implementation of detection algorithm for receiver in narrowband IoT channel |
| ZHANG Xin,WANG Yu,SHAN Rui,WANG Yi,WU Haoyue |
| (School of Electronic Engineering，Xi′an University of Posts and
Telecommunications,Xi′an 710121,China;School of Computer，Xi′an University of Posts and
Telecommunications,Xi′an 710121,China) |
| Abstract: |
| In allusion to the problems from detection and arrival time in narrow band Internet of Things（NB-IoT）physical random access channel(PRACH),such as algorithmic large amount of data calculation and time-consuming,a parallelization hardware implementation scheme based on reconfigurable array processor is proposed by analyzing the parallelism and data correlation of receiver detection algorithms.When the preamble symbols generated by the high-level configuration parameters and the received symbols processed by the previous channel have the maximum correlation,the algorithm uses the arrival time and the residual subcarrier offset as estimation indexes,and uses multiple light-core processor element(PE) in a pipelined manner to realize parallel computation to improve the operation efficiency.The experimental results show that the mapping of the algorithm is realized by using 6 PE's simultaneous scheduling,which runs for 35 985 cycles,and its performance is 36.18% higher than that of a single PE.Compared with the running time of the algorithm on Matlab,the design scheme reduces 173.09 times,which effectively improves the operation efficiency of the receiving end detection algorithm. |
| Key words: narrowband Internet of Things receiver detection reconfigurable array processor physical random access channel |
《电讯技术》编辑部 