| 摘要: |
| 为解决毫米波通信系统中数据速率和频谱资源紧张的难题，采用直接数字频率合成(DDS)和锁相环(PLL)技术，基于改进的π/4-QPSK调制方式，以现场可编程门阵列（FPGA）为控制单元，设计了一种用于毫米波通信系统的QPSK调制器。重点介绍了应用FPGA实现Gold码的编码过程，并给出了Gold编码Modelsim仿真结果。测试结果表明，该毫米波调制器工作稳定，QPSK调制信号中心频率30 GHz，数据速率3 Gb/s，输出功率大于4 dBm，相位噪声优于-100 dBc/Hz@10 kHz，可用于实际工程。 |
| 关键词: 毫米波通信系统 QPSK调制器 直接数字频率合成 Gold码 锁相环 |
| DOI： |
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| 基金项目:四川省教育厅重点项目（13ZA0087） |
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| Design of a QPSK modulator for millimeter wave communication system |
| HUANG Gang,CHEN Changming |
| () |
| Abstract: |
| In order to solve the problem of low data rate and short spectrum resource in millimeter wave(MMW) communication system,a quadrature phase shift keying(QPSK) modulator is implemented with direct digital synthesis(DDS) and phase-locked loop(PLL) technology .This system′s modulation is based on π/4-QPSK and controlled unit is implemented with Field Programmable Gate Array(FPGA). Especially,the realization of Gold code encoding process by FPGA is introduced,and the result of Gold code Modelsim simulation is given. The measured results show that system works stable and frequency centers 30 GHz,data rate is 3 Gb/s,output power is greater than 4 dBm and phase noise level is better than -100 dBc/Hz at 10 kHz offset frequency. This MMW QPSK modulator can be used in practical engineering. |
| Key words: millimeter wave communication system QPSK modulator direct digital synthesis Gold code phase-locked loop |
《电讯技术》编辑部 