| 摘要: |
| 介绍了小数式锁相频率合成器的设计方法及相关理论,分析了影响锁相环相位噪声的主要因素并设计了环路滤波器和Wilkinson功率分配器。由实验结果可知,小数式锁相频率合成器具有很好的相位噪声和较高的频率分辨率。 |
| 关键词: 频率合成器,锁相环,相位噪声,小数分频 |
| DOI： |
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| 基金项目: |
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| Design of an S Band Phase Locked Loop Frequency Synthesizer |
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| Abstract: |
| The design method and correlated principles of fractional-N phase locked loop (PLL) frequency synthesizer are described. The factors that affect the phase noise are analyzed and the loop filter and the Wilkinson power divider are designed. The test result proves that the design has such advantages as good phase noise and high resolution. |
| Key words: frequency synthesizer,phase locked loop,phase noise,fractional-N |
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