| 摘要: |
| 分析了DDS原理、CORDIC原理及其一种改进方法,设计了基于改进CORDIC算法的流水线QDDS系统,在Altera公司的ACEX1K-EP1K50TC144-1芯片上予以实现,通过对数据的频谱分析验证了系统工作性能.系统输入频率控制字32位,输出幅度位数16位,最高工作频率83.33 MHz,频率转换时间440 ns,频率分辨率0.0196 Hz,杂散指标-114 dB. |
| 关键词: CORDIC算法 QDDS FPGA 流水线 |
| DOI：10.3969/j.issn.1001-893X. |
| 投稿时间：2006-03-01修订日期：2006-06-05 |
| 基金项目: |
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| FPGA Implementation and Accuracy Analysis of QDDS Based on Ameliorated CORDIC Algorithm |
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| Abstract: |
| The principle of DDS, CORDIC and its amelioration are analyzed, the pipeline QDDS system based on the ameliorated CORDIC algorithm is designed, and is implemented on the ACEX1K- EP1K50TC144- 1 chip of the Altera company. The capability of the system is verified through the spectrum analysis of the data. The input frequency control word is 32bit, the output amplitude is 16bit, the highest operating frequency is 83.33 MHz, the time of the frequency conversion is 440 nanosecond, the frequency resolution is 0.0196Hz,the highest spurious is -ll4dB. |
| Key words: CORDIC algorithm,quadrature direct digital synthesis(QDDS),FPGA,pipeline |
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