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引用本文：

彭来献,路欣,赵文栋,田畅.一种太比特路由器交换核心的研究与设计[J].电讯技术，2006，46（6）：122 - 127. [点击复制]
.Research on and Design of a Novel Switch Core for Terabit Routers[J].，2006，46（6）：122 - 127. [点击复制]

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一种太比特路由器交换核心的研究与设计

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摘要:

硬件可扩展性和高效的性能一直以来是高速交换核心设计中的一对矛盾。文中在总结高速交换核心关键技术之后，提出了一种基于iRGRR算法的高速交换核心，它具有硬件实现简单、可扩展性强、性能优良等特点，大大缓解了上述矛盾。该交换核心能够提供服务质量保证，支持IP分组调度。可应用于太比特路由器中。文中还简要分析了该交换核心的性能，并给出了硬件设计方案。

关键词: 路由器交换核心输入排队 iRGRR算法可扩展性

DOI：10.3969/j.issn.1001-893X.

投稿时间：2006-03-28修订日期：2006-06-08

基金项目:

Research on and Design of a Novel Switch Core for Terabit Routers

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Abstract:

In the design of high-speed switch cores,there has existed a contradiction between scalability in hardware and efficient performance.After summarizing the key technologies of high-speed switch cores,a novel switch core based on iRGRR(iterative request-grant-based round-robin) scheduling algorithm is presented.This switch core has many good features,such as simple,scalability and fine performance,and its appearance greatly relaxes the contradiction mentioned above.The switch core can also provide quality of service guarantees and support scheduling of IP packets,so it can be used in terabit routers.The performance of the switch core is also analysed,and hardware design scheme is given.

Key words: router,switch core,input-queued,iterative request-grant-based round-robin(iRGRR) algorithm,scalability