| 摘要: |
| 研究了高速多入多出（MIMO）解调器的实时实现，并且基于一种与信道译码器联合迭代的MIMO检测算法，提出了高效可行的FPGA实现方案。仿真分析和实验表明，硬件实现的性能与理论性能接近。完全可应用于新一代移动通信系统中完成高速MIMO解调的任务。 |
| 关键词: 垂直-贝尔实验室分层空时码 多入多出 解调器 |
| DOI：10.3969/j.issn.1001-893X. |
| 投稿时间：2006-02-21修订日期：2006-06-20 |
| 基金项目:国家自然科学基金;国家高技术研究发展计划(863计划) |
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| Implementation of a High Rate MIMO Demodulator with FPGAs |
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| Abstract: |
| The implementation of a MIMO demodulator is investigated. An effective and feasible implementation with FPGAs based on a Turbo MIMO detection algorithm is developed. Analysis and simulation shows that the BER performance of FPGA implementation is very close to that of theoretic model. This MIMO demodulator can meet high date rate requirement in next - G systems. |
| Key words: B3G FPGA |
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