| 摘要: |
| 随着FPGA技术的稳步提高，FPGA替代其他技术用于实现高速信号处理已经变得切实可行。针对高阶FIR滤波器十分消耗FPGA硬件资源的问题，提出了一种采用基于位级联的多查找表分布式算法，并以一个32阶8位低通FIR滤波器为例，验证了所提出的方法。仿真结果表明，采用这种方法大大减少了FPGA硬件资源的耗费。 |
| 关键词: 数字信号处理 FIR数字滤波器,分布式算法,FPGA,查找表 |
| DOI：10.3969/j.issn.1001-893X. |
| 投稿时间：2004-11-04修订日期：2005-02-02 |
| 基金项目:重庆市科委应用基础项目 |
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| High Order FIR Filter Based on Distributed Arithmetic and Its FPGA Implementation |
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| Abstract: |
| As Field Programmable Gate Array(FPGA) technology has been steadily improved, FPGAs are now viable alternatives to other technology implementations for high-speed classes of digital signal processing(DSP) application. To solve the problem that implementation of high order FIR filter consumes rather more hardware resources in FPGA, the bit-serial distributed arithmetic based on multiple look-up tables is presented. A 32-tap 8-bit order low pass FIR filter is taken as an example to illustrate the method. Simulation shows that the method saves much more resources in FPGA,and improves the performance of FIR filter to some extent. |
| Key words: digital signal processing FIR digital filter distributed arithmetic FPGA look -up table |
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