| 摘要: |
| 给出了一种用于第三代移动通信系统(3G)CDMA2000基站的时钟同步方案。由一个双星接收卡接收GPS/GLONASS标准秒信号作为整个时钟同步系统的参考,分两级锁相环实现:第一级锁相环采用软件锁相,输出10MHz信号作为第二级锁相环的参考源,第二级锁相环为2个模拟锁相环,分别输出16fc和48fc(fc=1.2288MHz)。2S信号由16fc分频得到。这种设计保证了输出时钟的长期稳定性和短期稳定性,满足协议所规定的同步精度。详细介绍了数字鉴相器、2S产生电路、相差检测及控制电路的电路设计和有关仿真结果。 |
| 关键词: GPS/GLONASS,时钟同步,锁相环,恒温晶振,鉴相,分频 |
| DOI：10.3969/j.issn.1001-893X. |
| 修订日期：2003-01-17 |
| 基金项目:广东省自然科学基金资助项目(000840) |
|
| Programmable Logic Implementation of GPS/GLONASS Synchronization in CDMA2000 Base Station |
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| Abstract: |
| A clock synchronization scheme of 3G mobile communication systemCDMA2000 is presented. The PPS signal received by a GPS/GLONASS receiving card is regarded as a reference of the whole clock synchronization system that is consist of two levels PLL: the first one uses software implementation and its output 10MHz clock is taken as the reference of the second one. The second level PLL is comprised of two PLLs and outputs 16f_c and 48f_c(f_c=1.2288MHz).The 2S signal is obtained by 16f_c dividing frequency. Both the long term stability and the short term stability of the output clocks are assured by this scheme and the synchronization requests of the protocol are contented. Then the circuits and the modeling results of the digital phase detector, the 2S generating module and the phase detecting and controlling module are presented. |
| Key words: GPS/GLONASS,Clock synchronization,PLL,OCXO,Phase detecting,Frequency dividing |
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