| 摘要: |
| 论文阐述了１００ＭＨｚ数字锁相环的设计过程，用１０ＭＨｚ晶体振荡器对１００ＭＨｚ数字压控振荡器进行锁相，使１００ＭＨｚ输出信号指标得到很大改善。论文还分析了各单元电路，关键点时域波形测试，频谱测试。 |
| 关键词: 信号源 数字锁相环 压控振荡器 高频电路 |
| DOI：10.3969/j.issn.1001-893X. |
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| 基金项目: |
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| The Study of High Frequency Digital PLL |
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| Abstract: |
| The design of 100 MHz digital PLL is discussed in the paper.a 100 MHz digital PLL source,locked to a 10 MHz crystal oscillator,is one workable way that can improve the character of the 100 MHz source.Some parts of circuit is anslysed,still,some key points of the system are tested in both time and frequency domain. |
| Key words: Source,Digital PLL,Digital VCO,High Frequency Circuit, |
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